Multiplier device with suppression of higher-order distortion

ABSTRACT

A multiplier device is configured to include first to n th  multipliers M 1  to M n  for multiplying a carrier modulated information signal with first to n th  mutually phase shifted and identical, substantially square wave mixing signals MS 1  to MS n  with 50% duty cycle. In order to eliminate fifth or higher order interferences from the output of the multiplier device according to the invention, n is greater than 2, outputs of the multipliers M 1  to M n  are respectively coupled through weighting circuits W 1  to W n  with respective fixed weighting factors WF 1  to WF n  to an adder circuit, the mixing signals MS 1  to MS n  having respective phase angles φ i  corresponding to φ i =i*Δφ, the weighting factors WF i  corresponding to the sine value of the respective phase angles φ i =i*Δφ with Δφ being the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n+1) and i varying from 1 to n.

This application is a continuation of U.S. patent application Ser. No. 10/581,659, filed 31 May 2006, and claims the benefit of PCT/EP2004/013742, filed 1 Dec. 2004 and EP 03078812, filed 5 Dec. 2003.

BACKGROUND AND SUMMARY OF THE INVENTION

The invention relates to a multiplier device comprising first to n^(th) multipliers M₁ to M_(n) for multiplying a carrier modulated information signal with first to n^(th) mutually phase shifted and identical, substantially square wave mixing signals MS₁ to MS_(n) with 50% duty cycle. Such multiplier devices are frequently used in receivers for converting an RF antenna input signal with an RF carrier frequency f_(RF) into an intermediate frequency (IF) signal with an IF carrier frequency f_(IF) and/or for demodulating an (IF) carrier modulated information signal with carrier frequency fc into baseband, or as used in stereo decoder circuits for decoding and/or demultiplexing a stereo multiplex signal into left and right baseband stereo signals.

A stereo decoder circuit using such multiplier device to demodulate a stereo difference signal (L−R) double sideband amplitude modulated on a subcarrier fc of 38 kHz into baseband, is e.g. known from U.S. Pat. No. 3,962,551. This known multiplier device comprises first and second multipliers M₁ and M₂, receiving the stereo difference signal (L−R) modulated 38 kHz subcarrier as well as respectively first and second identical, substantially square wave mixing signals MS₁ and MS₂ having a 38 kHz repetition or mixing frequency fo=fc and 50% duty cycle, mutually differing in phase by a phase angle Δφ of 60 degree. The mixing of the subcarrier modulated stereo difference signal (L−R) with the first and second mixing signals MS₁ and MS₂ will result not only in the wanted stereo difference signal (L−R), but also any undesired information signal in the region of 3fo=114 KHz being demodulated into baseband, due to the third order harmonic components 3fo of the mixing signals MS₁ and MS₂. However, the so obtained undesired baseband information signal occurring in the output signal of the first multiplier M₁ is identical but phase opposite to the undesired baseband information signal occurring in the output signal of the second multiplier M₂, hereinafter being referred to as third order interferences. By using an adder circuit following upon the first and second multipliers an addition of the wanted stereo difference signals (L−R) simultaneously with a compensation of the unwanted third order interference at the outputs of the first and second multipliers M₁ and M₁ is being obtained. The adder circuit therewith delivers the desired baseband stereo difference signals (L−R) free from unwanted third order interferences.

In practice, this known multiplier device appears to maintain its suppression of third order interferences when being used with a mixing frequency fo deviating from the carrier frequency fc, also at relatively high values of fc and/or fo causing the waveform of the mixing signals to deviate considerably from rectangular. This provided that the mutually identical correspondence in waveforms and the 50% duty cycle of the first and second mixing signals MS₁ and MS₂ are preserved.

However, due to the ongoing demand for higher performance/price ratio the suppression of third order interferences as provided for in the above known multiplier device does not suffice anymore.

On itself, a stereo decoder is known from U.S. Pat. No. 5,220,607, in which third and fifth order harmonic interferences are prevented from occurring in the output signal of a multiplier device by using a mixing signal having a specifically defined, rectangular multi-level waveform. This known interference suppression depends on the accuracy in maintaining the specific waveform. At frequencies increasing above the 38 kHz stereo difference signal (L−R) subcarrier frequency the waveform will be deteriorated by increasing non-linearities, making this known interference suppression unsuitable for receiver applications.

It is an object of the present invention to provide a robust, low cost multiplier device allowing for an effective suppression of all undesired higher order interferences, which is very well suitable for use in receivers for converting an RF antenna input signal into an IF signal.

Another object of the invention is to allow for a robust and low cost implementation.

Now, therefore, a multiplier device comprising first to n^(th) multipliers M₁ to M_(n) for multiplying a carrier modulated information signal with first to n^(th) mutually phase shifted and identical, substantially square wave mixing signals MS₁ to MS_(n) with 50% duty cycle according to the invention is characterized by n being greater than 2, outputs of the multipliers M₁ to M_(n) being respectively coupled through weighting circuits W₁ to W_(n) with respective fixed weighting factors WF₁ to WF_(n) to an adder circuit, the mixing signals MS₁ to MS_(n) having respective phase angles φ_(i) corresponding to φ_(i)=i*Δφ, the weighting factors WF_(i) corresponding to the sine value of the respective phase angles φ_(i)=i*Δφ with Δφ being the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n+1) and i varying from 1 to n.

The invention is based on the insight that cancellation of interferences of any higher order in a multiplier device can be obtained with a properly chosen number n of multipliers and same number of mutually identical mixing signals with 50% duty cycle by using only the multiplication gains and phase angles of the mixing signals as parameters.

By applying the above measure according to the invention, the mutually identical 50% duty cycle waveform of the n mixing signals are chosen to be substantially rectangular, allowing for a multiple use of mutually identical cost effective non-linear multipliers, logic and other circuitry and adequate operation at high frequencies. The multiplication gains are being provided for with the weighting circuits W₁ to W_(n) allowing for the use of mutually identical multipliers with mutually identical gain, which are easy to implement.

By choosing the mutual phase shift between the mixing signals and the weighting factors WF₁ to WF_(n) of the weighting circuits W₁ to W_(n) in accordance with the above the above measure according to the invention harmonic interferences up to the (2n−1) order are being suppressed. Or, vice versa, by choosing the number n to correspond to (N+1)/2 an elimination of all harmonics up to the N^(th) order from the output of the adder circuit in accordance with the invention is obtained.

Another preferred embodiment of a multiplier device according to the invention which allows for a cost effective implementation is characterized by the mixing signals MS₁ to MS_(n) being derived from a local oscillator signal with frequency fo through an arrangement of fixed phase shift means and/or frequency divider means.

A robust and accurate implementation of an embodiment of a multiplier device according to the invention is characterized by a local oscillator circuit supplying an oscillator signal with frequency fo to a serial arrangement of first to n^(th) phase shifting means, each providing a fixed phase shift of Δφ and supplying respectively mixing signals MS₁ to MS_(n) to the first to n^(th) multipliers M₁ to M_(n).

Preferably, the local oscillator circuit generates a clock control signal with clock frequency n*fo being supplied through a frequency divider with dividing factor n to the serial arrangement of first to n^(th) phase shifting means, each of the first to n^(th) phase shifting means comprising a D-flip-flop being clock controlled by the clock control signal and providing the fixed phase shift of Δφ.

BRIEF DESCRIPTION OF THE DRAWINGS

These and further aspects and advantages of the invention will be discussed more in detail hereinafter with reference to the disclosure of preferred embodiments, and in particular with reference to the appended Figures that show:

FIG. 1, a multiplier device according to the invention;

FIG. 2A, a graph for deriving the mutual phase difference between two phase consecutive mixing signals and weighting factors WF1 to WF3 in a multiplier device according to the invention for n=3;

FIGS. 2B to 2D, waveforms of identical, substantially square wave mixing signals MS₁ to MS₃ with 50% duty cycle for n=3;

FIG. 3A, a graph for deriving the mutual phase difference between two phase consecutive mixing signals and weighting factors WF1 to WF4 in a multiplier device according to the invention for n=4;

FIGS. 3B to 3D, waveforms of identical, substantially square wave mixing signals MS₁ to MS_(n) with 50% duty cycle for n=4;

FIG. 4A, a mixing signal generator for generating first to n^(th) mutually phase shifted and identical, substantially square wave mixing signals MS₁ to MS_(n) with 50% duty cycle according to the invention;

FIG. 4B, deviations of mixing signals, which do not affect proper operation of the multiplier device according to the invention.

DETAILED DESCRIPTION

FIG. 1 shows an embodiment of a multiplier device (M1-Mn, W1-Wn, ADD) according to the invention used in a receiver front end. The receiver front end comprises an RF antenna ANT being coupled to an RF input unit RFI supplying an RF antenna input signal with an RF carrier frequency f_(RF) in common to first to n^(th) multipliers M₁ to M_(n), n being 3 or more. The RF antenna input signal is being demodulated therein into an intermediate frequency (IF) signal with an IF carrier frequency f_(IF). The first to n^(th) multipliers M₁ to M_(n) receive from a mixing signal generator MSG respectively first to n^(th) mutually phase shifted and identical, substantially square wave mixing signals MS₁ to MS_(n) with 50% duty cycle. Outputs of the first to n^(th) multipliers M₁ to M_(n) are respectively coupled through weighting circuits W₁ to W_(n) with respective fixed weighting factors WF₁ to WF_(n) to an adder circuit ADD. The adder circuit ADD provides at its output the IF signal without harmonic interferences up to the (2n−1)^(th) order. According to the invention, the mixing signals MS₁ to MS_(n) have respective phase angles φ_(i) corresponding to φ_(i)=i*Δφ, whereas the weighting factors WF_(i) correspond to the sine value of the respective phase angles φ_(i)=i*Δφ with Δφ being the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n+1) and i varying from 1 to n.

By choosing n to correspond to (N+1)/2, elimination of all harmonics up to the N^(th) order from the output of the adder circuit ADD is obtained.

FIG. 2A shows how to determine the mutual phase difference between two phase consecutive mixing signals and the weighting factors WF1 to WF3 in a multiplier device according to the invention for an elimination of the third, fifth and seventh order harmonic interferences, i.e. for n=3.

FIGS. 2B to 2D show respectively first to third mutually identical, substantially square wave mixing signals MS₁ to MS₃ with 50% duty cycle having respective phase angles φ₁ to φ₃ corresponding to Δφ, 2Δφ and 3Δφ. Herein Δφ is the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n+1), for n=3 being π/4. The weighting factors WF₁ to WF₃ correspond to the sine value of the respective phase angles φ₁ to φ₃, i.e. sin π/4, sin π/2 and sin 3π/4 or 0.7, 1 and 0.7.

The use of these mixing signals MS₁ to MS₃ with Δφ being π/4 and weighting factors WF₁ to WF₃ equalizing respectively 0.7, 1 and 0.7, causes all higher order harmonic interferences up to the fifth order to be eliminated from the output signal of the adder circuit ADD.

FIG. 3A shows how to determine the mutual phase difference between two phase consecutive mixing signals and the weighting factors WF1 to WF4 in a multiplier device according to the invention for an elimination of the third, fifth and seventh order harmonic interferences, i.e. for n=4.

FIGS. 3B to 3D show respectively first to fourth mutually identical, substantially square wave mixing signals MS₁ to MS₄ with 50% duty cycle having respective phase angles φ₁ to φ₄ corresponding to Δφ, 2Δφ, 3Δφ and 4Δφ. Herein Δφ is the mutual phase difference between each two phase consecutive mixing signals corresponding to π/(n+1), for n=4 being π/5. The weighting factors WF₁ to WF₄ correspond to the sine value of the respective phase angles φ₁ to φ₄, i.e. sin π/5, sin 2π/5, sin 3π/5 and sin 4π/5 or 0.59, 0.95, 0.95 and 0.59.

The use of these mixing signals MS₁ to MS₄ with Δφ being π/5 and weighting factors WF₁ to WF₄ equalizing respectively 0.59, 0.95, 0.95 and 0.59 0.7, 1 and 0.7, causes all higher order harmonic interferences up to the ninth order to be eliminated from the output signal of the adder circuit ADD.

FIG. 4 A shows an embodiment of a mixing signal generator MSG as used in the mixer device of FIG. 1, comprising a local oscillator circuit LOC generating a clock control signal with clock frequency n*fo being supplied through a frequency divider FD with dividing factor n to a serial arrangement of first to n^(th) phase shifting means, each of the first to n^(th) phase shifting means D1 to Dn, comprising a D-flip-flop being clock controlled by the clock control signal and providing the fixed phase shift of Δφ. Mixing signals MS₁ to MS_(n) are being supplied from respectively outputs of the first to n^(th) phase shifting means D1 to Dn to the first to n^(th) multipliers M₁ to M_(n).

FIG. 4B shows a mixing signal waveform which deviates from rectangular due to the smoothing effect of one (bold line) or two (bold and dotted lines) time constants occurring at high frequencies. Such substantially square waveform mixing signals do not jeopardize the suppression of undesired higher order harmonic interferences in a multiplier device according to the invention provided they are mutually identical.

In the above, the present invention has been described with reference to a disclosure and drawings that illustrate a preferred embodiment. Persons skilled in the art would however from inspecting thereof recognize various changes and amendments to such preferred embodiment. For example, the mixing signal generator MSG may well use other configurations of delay circuits and/or frequency dividers to obtain the above mixing signals according to the invention.

Therefore, the disclosure herein should be considered by way of example, rather than by way of restriction, and the due scope of the present invention should be determined from the claims appended hereto.

In interpreting these claims, it should be understood that:

a) the word “comprising” does not exclude the presence of other elements or acts than those listed in a given claim;

b) the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements;

c) any reference signs in the claims do not limit their scope;

d) several “means” may be represented by the same item or hardware or software implemented structure or function;

e) each of the disclosed elements may be comprised of hardware portions (e.g., including discrete and integrated electronic circuitry), software portions (e.g., computer programming), and any combination thereof,

f) hardware portions may be comprised of one or both of analog and digital portions;

g) any of the disclosed devices or portions thereof may be combined together or separated into further portions unless specifically stated otherwise;

h) no specific sequence of acts is intended to be required unless specifically indicated; and

i) the term “plurality of” an element includes two or more of the claimed element, and does not imply any particular range of number of elements; that is, a plurality of elements can be as few as two elements, and can include an immeasurable number of elements. 

1. A method for execution in a signal processing system comprising: receiving an input signal; generating a number of mixing signals, the number of mixing signals being greater than two, each mixing signal having a common frequency and different phase; multiplying the input signal by each of the mixing signals to produce a plurality of intermediate signals, and combining all of the intermediate signals to provide an output signal.
 2. The method of claim 1, wherein the combining includes providing a weighted sum of the intermediate signals.
 3. The method of claim 2, wherein each intermediate signal has a weight for determining the weighted sum that corresponds to a sine of the phase of the corresponding mixing signal.
 4. The method of claim 3, wherein each mixing signal has a 50% duty cycle.
 5. The method of claim 4, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 6. The method of claim 3, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 7. The method of claim 2, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 8. The method of claim 1, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 9. The method of claim 1, wherein generating the mixing signals includes generating a local oscillator signal, delaying the local oscillator signal via a string of delay devices, wherein each mixing signal corresponds to an output of each delay device.
 10. The method of claim 9, wherein each delay device delays the local oscillator signal by P/2(n+1), where P corresponds to a period of the local oscillator signal, and n equals the number of mixing signals.
 11. The method of claim 9, wherein generating the mixing signal includes dividing the local oscillator signal by a factor of n to provide a clocking signal, where n equals the number of mixing signals, and clocking each of the delay devices with the clocking signal to provide each of the mixing signals.
 12. A computer program stored on a computer-readable medium that, when executed by a signal processor, causes the processor to: receive an input signal; generate a number of mixing signals, the number of mixing signals being greater than two, each mixing signal having a common frequency and different phase; multiply the input signal by each of the mixing signals to produce a plurality of intermediate signals, and combine all of the intermediate signals to provide an output signal.
 13. The program of claim 12, wherein the program is configured to cause the processor to combine the intermediate signals by accumulating a weighted sum of the intermediate signals.
 14. The program of claim 13, wherein each intermediate signal has an associated weight for accumulating the weighted sum that corresponds to a sine of the phase of the corresponding mixing signal.
 15. The program of claim 14, wherein each mixing signal has a 50% duty cycle.
 16. The program of claim 15, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 17. The program of claim 14, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 18. The program of claim 13, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 19. The program of claim 12, wherein each mixing signal differs in phase from another mixing signal by π/(n+1), where n equals the number of mixing signals.
 20. The program of claim 12, wherein the processor is configured to receive a local oscillator signal, and the program is configured to cause the processor to generate each mixing signal via a series of delays, each delay being substantially equal to P/2(n+1), where P corresponds to a period of the local oscillator signal, and n equals the number of mixing signals. 